A semiconductor chip mounted on an electronic device has been required to be more highly integrated in order to respond to requirements such as saving of a mounting area, improvement in processing rate, suppression of power consumption, and multi-functionalization.
A three-dimensional semiconductor chip has been developed in order to obtain high integration (for example, Patent Document 1).
That is, in the three-dimensional semiconductor chip, multiple semiconductor chips are stacked and the stacked semiconductor chips are wiring-connected, so that the high integration of the integrated circuit is obtained. As for each semiconductor chip used in the three-dimensional semiconductor chip, both sides of a chip plate need to be electrically connected. Therefore, conventionally, there has been employed, for example, a buried wiring in which a through-hole is formed in the semiconductor chip and a conductive member is buried within the through-hole.
As a specific method for forming such the buried wiring, there has been considered, for example, a method in which a coupling agent is adsorbed onto an entire substrate including a hole, and then, an underlying processing layer of W, WN, Ta, or TaN is formed by a CVD method or a PVD method, or a coupling agent is adsorbed onto an entire substrate including a hole and then, an underlying processing layer of an alloy including Ni, Co, WNi, or WCo, or another alloy including P or B with any one of them is formed by an electroless plating method.
Then, an electroless copper plating layer is formed on underlying processing layer by performing an electroless reduction plating process (Patent Document 2).
However, if an underlying layer is formed on a substrate and then, an electroless plating layer is formed on the underlying layer by performing the electroless reduction plating process as such, the underlying layer and the electroless plating layer are likely to be peeled off from the substrate. Thus, during an electroless plating process or during a CMP (Chemical Mechanical Polishing) process as a post-treatment, the underlying layer and the electroless plating layer may be peeled off from the substrate.
Patent Document 1: Japanese Patent Laid-open Publication No. 2003-203914
Patent Document 2: Japanese Patent Laid-open Publication No. 2012-216722